Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
Table 37. SGMII DC Transmitter Electrical Characteristics (continued)
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Change in V between “0” and “1”
Δ V
—
—
—
—
25
40
mV
mA
—
—
OS
OS
Output current on short to GND
I
, I
SA SB
Note:
1. This will not align to DC-coupled SGMII. XV
=1.1 V.
DD_SRDS2-Typ
2. |V | = |V
- V
|. |V | is also referred as output differential peak voltage. V
= 2*|V |
OD .
OD
SD2_TXn
SD2_TXn
OD
TX-DIFFp-p
3. The |V | value shown in the table assumes the following transmit equalization setting in the XMITEQAB (for SerDes 2 lanes
OD
A & B) or XMITEQEF (for SerDes 2 lanes E & E) bit field of MPC8572E’s SerDes 2 Control Register:
•The MSbit (bit 0) of the above bit field is set to zero (selecting the full V
amplitude - power up default);
DD-DIFF-p-p
•The LSbits (bit [1:3]) of the above bit field is set based on the equalization setting shown in table.
4. V is also referred to as output common mode voltage.
OS
•
5.The |V | value shown in the Typ column is based on the condition of XV
=1.1V, no common mode offset
OD
DD_SRDS2-Typ
variation (V =550mV), SerDes2 transmitter is terminated with 100-Ω differential load between SD2_TX[n] and
OS
SD2_TX[n].
SD2_TXn
SD_RXm
SD_RXm
50 Ω
50 Ω
C
C
TX
50 Ω
50 Ω
Receiver
Transmitter
TX
SD2_TXn
SD2_RXn
MPC8572E SGMII
SerDes Interface
C
SD_TXm
50 Ω
TX
50 Ω
50 Ω
Receiver
Transmitter
50 Ω
C
TX
SD2_RXn
SD_TXm
Figure 22. 4-Wire AC-Coupled SGMII Serial Link Connection Example
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
45
FREESCALE [ Freescale ]
