Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
Figure 17 shows the TBI receive the timing diagram.
t
TRRR
t
TRR
RX_CLK
RCG[9:0]
t
TRRH
t
TRRF
valid data
t
t
TRRDV
TRRDX
Figure 17. TBI Single-Clock Mode Receive AC Timing Diagram
8.2.6
RGMII and RTBI AC Timing Specifications
Table 33 presents the RGMII and RTBI AC timing specifications.
Table 33. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with LVDD/TVDD of 2.5 V ± 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)
t
t
–500
1.0
7.2
40
0
—
8.0
50
—
—
500
2.8
ps
ns
ns
%
SKRGT
2
Data to clock input skew (at receiver)
SKRGT
3
Clock period
t
8.8
RGT
3, 4
Duty cycle for 10BASE-T and 100BASE-TX
Rise time (20%–80%)
Fall time (20%–80%)
t
/t
60
RGTH RGT
t
—
0.75
0.75
ns
ns
RGTR
t
—
RGTF
Notes:
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent
RGMII and RTBI timing. For example, the subscript of t represents the TBI (T) receive (RX) clock. Note also that the
RGT
notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the
subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns will
be added to the associated clock signal.
3. For 10 and 100 Mbps, t
scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
RGT
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
as the minimum duty cycle is not violated and stretching occurs for no more than three t
between.
of the lowest speed transitioned
RGT
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
39
FREESCALE [ Freescale ]
