Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
Table 35. RMII Receive AC Timing Specifications (continued)
At recommended operating conditions with LVDD/TVDD of 2.5/ 3.3 V ± 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
RXD[1:0], CRS_DV, RX_ER hold time to
TSECn_TX_CLK rising edge
t
2.0
—
—
ns
RMRDX
Note:
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes MII receive
(first two letters of functional block)(reference)(state)(signal)(state)
MRDVKH
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
clock reference (K)
MRX
going to the high (H) state or setup time. Also, t
symbolizes MII receive timing (GR) with respect to the time data input
MRDXKL
signals (D) went invalid (X) relative to the t
clock reference (K) going to the low (L) state or hold time. Note that, in general,
MRX
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For
example, the subscript of t represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used
MRX
with the appropriate letter: R (rise) or F (fall).
Figure 20 provides the AC test load for eTSEC.
LV /2
Output
Z = 50 Ω
0
DD
R = 50 Ω
L
Figure 20. eTSEC AC Test Load
Figure 21 shows the RMII receive AC timing diagram.
t
t
RMRR
RMR
TSECn_TX_CLK
t
t
RMRF
RMRH
RXD[1:0]
CRS_DV
RX_ER
Valid Data
t
RMRDV
t
RMRDX
Figure 21. RMII Receive AC Timing Diagram
8.3
SGMII Interface Electrical Characteristics
Each SGMII port features a 4-wire AC-Coupled serial link from the dedicated SerDes 2 interface of
MPC8572E as shown in Figure 22, where C is the external (on board) AC-Coupled capacitor. Each
TX
output pin of the SerDes transmitter differential pair features 50-Ω output impedance. Each input of the
SerDes receiver differential pair features 50-Ω on-die termination to SGND_SRDS2 (xcorevss). The
reference circuit of the SerDes transmitter and receiver is shown in Figure 54.
When an eTSEC port is configured to operate in SGMII mode, the parallel interface’s output signals of
this eTSEC port can be left floating. The input signals should be terminated based on the guidelines
described in Section 21.5, “Connection Recommendations,” as long as such termination does not violate
the desired POR configuration requirement on these pins, if applicable.
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
42
Freescale Semiconductor
FREESCALE [ Freescale ]
