Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
Figure 18 shows the RGMII and RTBI AC timing and multiplexing diagrams.
t
RGT
t
RGTH
GTX_CLK
(At Transmitter)
t
SKRGT
TXD[8:5][3:0]
TXD[7:4][3:0]
TXD[8:5]
TXD[7:4]
TXD[3:0]
TXD[9]
TXERR
TXD[4]
TXEN
TX_CTL
t
SKRGT
TX_CLK
(At PHY)
RXD[8:5][3:0]
RXD[7:4][3:0]
RXD[8:5]
RXD[7:4]
RXD[3:0]
t
SKRGT
RXD[9]
RXERR
RXD[4]
RXDV
RX_CTL
t
SKRGT
RX_CLK
(At PHY)
Figure 18. RGMII and RTBI AC Timing and Multiplexing Diagrams
8.2.7
RMII AC Timing Specifications
This section describes the RMII transmit and receive AC timing specifications.
8.2.7.1
RMII Transmit AC Timing Specifications
Table 34 shows the RMII transmit AC timing specifications.
Table 34. RMII Transmit AC Timing Specifications
At recommended operating conditions with LVDD/TVDD of 2.5/ 3.3 V ± 5%.
Parameter/Condition Symbol
TSECn_TX_CLK clock period
1
Min
Typ
Max
Unit
t
15.0
35
20.0
50
—
25.0
65
ns
%
RMT
TSECn_TX_CLK duty cycle
t
RMTH
TSECn_TX_CLK peak-to-peak jitter
Rise time TSECn_TX_CLK (20%–80%)
Fall time TSECn_TX_CLK (80%–20%)
t
—
250
2.0
2.0
ps
ns
ns
RMTJ
t
1.0
1.0
—
RMTR
t
—
RMTF
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
40
FREESCALE [ Freescale ]
