Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
Figure 16 shows the TBI receive AC timing diagram.
t
t
TRX
TRXR
TBI Receive Clock 1
(TSECn_TX_CLK)
t
t
TRXH
TRXF
RCG[9:0]
Valid Data
Valid Data
t
TRDVKH
t
t
SKTRX
TRDXKH
TBI Receive Clock 0
(TSECn_RX_CLK)
t
t
TRXH
TRDXKH
t
TRDVKH
Figure 16. TBI Receive AC Timing Diagram
8.2.5
TBI Single-Clock Mode AC Specifications
When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant
eTSEC interface. In single-clock TBI mode, when a 125-MHz TBI receive clock is supplied on TSECn
pin (no receive clock is used in this mode, whereas for the dual-clock mode this is the PMA1 receive
clock). The 125-MHz transmit clock is applied in all TBI modes.
A summary of the single-clock TBI mode AC specifications for receive appears in Table 32.
Table 32. TBI single-clock Mode Receive AC Timing Specification
At recommended operating conditions with LVDD/TVDD of 2.5/ 3.3 V ± 5%.
Parameter/Condition
RX_CLK clock period
Symbol
Min
Typ
Max
Unit
t
7.5
40
—
8.0
50
—
—
—
—
—
8.5
60
ns
%
TRRX
RX_CLK duty cycle
t
/t
TRRH TRRX
RX_CLK peak-to-peak jitter
t
250
1.0
1.0
—
ps
ns
ns
ns
ns
TRRJ
Rise time RX_CLK (20%–80%)
Fall time RX_CLK (80%–20%)
RCG[9:0] setup time to RX_CLK rising edge
RCG[9:0] hold time to RX_CLK rising edge
t
—
TRRR
t
—
TRRF
t
2.0
1.0
TRRDVKH
TRRDXKH
t
—
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
38
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