Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
Figure 15 shows the TBI transmit AC timing diagram.
t
t
TTX
TTXR
GTX_CLK
TCG[9:0]
t
TTXH
t
TTXF
t
TTXF
t
t
TTXR
TTKHDV
t
TTKHDX
Figure 15. TBI Transmit AC Timing Diagram
8.2.4.2
TBI Receive AC Timing Specifications
Table 31 provides the TBI receive AC timing specifications.
Table 31. TBI Receive AC Timing Specifications
At recommended operating conditions with LVDD/TVDD of 2.5/ 3.3 V ± 5%.
3
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Clock period for TBI Receive Clock 0, 1
Skew for TBI Receive Clock 0, 1
t
—
16.0
—
—
8.5
60
—
ns
ns
%
TRX
t
7.5
40
SKTRX
Duty cycle for TBI Receive Clock 0, 1
t
/t
—
TRXH TRX
RCG[9:0] setup time to rising edge of TBI Receive Clock 0, 1
RCG[9:0] hold time to rising edge of TBI Receive Clock 0, 1
Clock rise time (20%-80%) for TBI Receive Clock 0, 1
Clock fall time (80%-20%) for TBI Receive Clock 0, 1
Notes:
t
2.5
1.5
0.7
0.7
—
ns
ns
ns
ns
TRDVKH
t
—
—
TRDXKH
2
t
—
2.4
2.4
TRXR
2
t
—
TRXF
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes TBI receive
clock reference (K) going
(first two letters of functional block)(reference)(state)(signal)(state)
TRDVKH
timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
TRX
to the high (H) state or setup time. Also, t
symbolizes TBI receive timing (TR) with respect to the time data input signals
TRDXKH
(D) went invalid (X) relative to the t
clock reference (K) going to the high (H) state. Note that, in general, the clock reference
TRX
symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of
represents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter:
t
TRX
R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX).
2. Guaranteed by design.
3. The signals “TBI Receive Clock 0” and “TBI Receive Clock 1” refer to TSECn_RX_CLK and TSECn_TX_CLK pins respectively.
These two clock signals are also referred as PMA_RX_CLK[0:1].
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
37
FREESCALE [ Freescale ]
