Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
Figure 14 shows the MII receive AC timing diagram.
t
t
MRXR
MRX
RX_CLK
t
t
MRXH
MRXF
RXD[3:0]
RX_DV
RX_ER
Valid Data
t
MRDVKH
t
MRDXKL
Figure 14. MII Receive AC Timing Diagram
8.2.4
TBI AC Timing Specifications
This section describes the TBI transmit and receive AC timing specifications.
8.2.4.1
TBI Transmit AC Timing Specifications
Table 30 provides the TBI transmit AC timing specifications.
Table 30. TBI Transmit AC Timing Specifications
At recommended operating conditions with LVDD/TVDD of 2.5/ 3.3 V ± 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
TCG[9:0] setup time GTX_CLK going high
TCG[9:0] hold time from GTX_CLK going high
GTX_CLK rise (20%–80%)
t
2.0
1.0
—
—
—
—
—
—
—
ns
ns
ns
ns
TTKHDV
t
TTKHDX
2
t
1.0
1.0
TTXR
2
GTX_CLK fall time (80%–20%)
t
—
TTXF
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state
for inputs and t
for outputs. For example,
(K) going high (H) until the
)(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
t
symbolizes the TBI transmit timing (TT) with respect to the time from t
TTKHDV
TTX
referenced data signals (D) reach the valid state (V) or setup time. Also, t
symbolizes the TBI transmit timing
TTKHDX
(TT) with respect to the time from t
(K) going high (H) until the referenced data signals (D) reach the invalid state
TTX
(X) or hold time. Note that, in general, the clock reference symbol representation is based on three letters
representing the clock of a particular functional. For example, the subscript of t represents the TBI (T) transmit
TTX
(TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. Guaranteed by design.
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
36
Freescale Semiconductor
FREESCALE [ Freescale ]
