Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
Figure 11 shows the GMII receive AC timing diagram.
t
t
GRXR
GRX
RX_CLK
t
t
GRXF
GRXH
RXD[7:0]
RX_DV
RX_ER
t
GRDXKH
t
GRDVKH
Figure 11. GMII Receive AC Timing Diagram
8.2.3
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.2.3.1
MII Transmit AC Timing Specifications
Table 28 provides the MII transmit AC timing specifications.
Table 28. MII Transmit AC Timing Specifications
At recommended operating conditions with LVDD/TVDD of 2.5/ 3.3 V ± 5%.
Parameter/Condition Symbol
TX_CLK clock period 10 Mbps
1
Min
Typ
Max
Unit
2
t
—
—
400
40
—
5
—
—
ns
ns
%
MTX
TX_CLK clock period 100 Mbps
TX_CLK duty cycle
t
MTX
t
t
35
1
65
15
4.0
4.0
MTXH/ MTX
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
TX_CLK data clock rise (20%-80%)
TX_CLK data clock fall (80%-20%)
Notes:
t
ns
ns
ns
MTKHDX
2
t
1.0
1.0
—
—
MTXR
2
t
MTXF
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes MII
(first two letters of functional block)(reference)(state)(signal)(state)
MTKHDX
transmit timing (MT) for the time t
clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in
MTX
general, the clock reference symbol representation is based on two to three letters representing the clock of a particular
functional. For example, the subscript of t represents the MII(M) transmit (TX) clock. For rise and fall times, the latter
MTX
convention is used with the appropriate letter: R (rise) or F (fall).
2. Guaranteed by design.
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
34
FREESCALE [ Freescale ]
