Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
Figure 9 shows the GMII transmit AC timing diagram.
t
t
GTX
GTXR
GTX_CLK
t
t
GTXF
GTXH
TXD[7:0]
TX_EN
TX_ER
t
GTKHDX
tG
TKHDV
Figure 9. GMII Transmit AC Timing Diagram
8.2.2.2
GMII Receive AC Timing Specifications
Table 27 provides the GMII receive AC timing specifications.
Table 27. GMII Receive AC Timing Specifications
At recommended operating conditions with LVDD/TVDD of 2.5/ 3.3 V ± 5%.
Parameter/Condition Symbol
RX_CLK clock period
1
Min
Typ
Max
Unit
t
—
40
2.0
0
8.0
—
—
—
—
—
—
60
—
ns
ns
ns
ns
ns
ns
GRX
RX_CLK duty cycle
t
/t
GRXH GRX
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise (20%-80%)
RX_CLK clock fall time (80%-20%)
Note:
t
GRDVKH
t
—
GRDXKH
2
t
—
—
1.0
1.0
GRXR
2
t
GRXF
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes GMII
(first two letters of functional block)(reference)(state)(signal)(state)
GRDVKH
receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the t clock
RX
reference (K) going to the high state (H) or setup time. Also, t
symbolizes GMII receive timing (GR) with respect to
GRDXKL
the time data input signals (D) went invalid (X) relative to the t
clock reference (K) going to the low (L) state or hold time.
GRX
Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For example, the subscript of t represents the GMII (G) receive (RX) clock. For rise and fall times, the latter
GRX
convention is used with the appropriate letter: R (rise) or F (fall).
2. Guaranteed by design.
Figure 10 provides the AC test load for eTSEC.
Output
Z = 50 Ω
0
LV /2
DD
R = 50 Ω
L
Figure 10. eTSEC AC Test Load
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
33