Package Description
Table 75. MPC8572E Pinout Listing (continued)
Signal Name Package Pin Number Pin Type
Power
Notes
Signal
Supply
TSEC1_TX_EN/FIFO1_TX_EN Transmit Enable
/FIFO1_TXC[0]
AJ24
AK25
O
O
LV
LV
1, 22
DD
DD
TSEC1_TX_ER/FIFO1_TX_ER Transmit Error
R/FIFO1_TXC[1]
1, 5, 9
Three-Speed Ethernet Controller 2
TSEC2_RXD[7:0]/FIFO2_RXD[ Receive Data
7:0]/FIFO1_RXD[15:8]
AG22, AH20, AL22,
AG20, AK21, AK22,
AJ21, AK20
I
LV
LV
1
DD
DD
TSEC2_TXD[7:0]/FIFO2_TXD[ Transmit Data
7:0]/FIFO1_TXD[15:8]
AH21, AF20, AC17,
AF21, AD18, AF22,
AE20, AB18
O
1, 5, 9, 24
TSEC2_COL/FIFO2_TX_FC
TSEC2_CRS/FIFO2_RX_FC
TSEC2_GTX_CLK
Collision Detect/Flow Control
AE19
AJ20
AE18
AL23
I
I/O
O
I
LV
LV
LV
LV
1
1, 16
—
DD
DD
DD
DD
Carrier Sense/Flow Control
Transmit Clock Out
TSEC2_RX_CLK/FIFO2_RX_C Receive Clock
LK
1
TSEC2_RX_DV/FIFO2_RX_DV Receive Data Valid
/FIFO1_RXC[2]
AJ22
AD19
AC19
AB19
AB17
I
I
LV
LV
LV
LV
LV
1
1
DD
DD
DD
DD
DD
TSEC2_RX_ER/FIFO2_RX_E Receive Data Error
R
TSEC2_TX_CLK/FIFO2_TX_C Transmit Clock In
LK
I
1
TSEC2_TX_EN/FIFO2_TX_EN Transmit Enable
/FIFO1_TXC[2]
O
O
1, 22
1, 5, 9
TSEC2_TX_ER/FIFO2_TX_ER Transmit Error
R
Three-Speed Ethernet Controller 3
TSEC3_TXD[3:0]/FEC_TXD[3: Transmit Data
0]/FIFO3_TXD[3:0]
AG18, AG17, AH17,
AH19
O
I
TV
TV
1, 5, 9
1
DD
DD
TSEC3_RXD[3:0]/FEC_RXD[3: Receive Data
0]/FIFO3_RXD[3:0]
AG16, AK19, AD16,
AJ19
TSEC3_GTX_CLK
Transmit Clock Out
AE17
AF17
O
I
TV
TV
DD
DD
TSEC3_RX_CLK/FEC_RX_CL Receive Clock
K/FIFO3_RX_CLK
1
1
1
TSEC3_RX_DV/FEC_RX_DV/F Receive Data Valid
IFO3_RX_DV
AG14
AH15
I
I
TV
TV
DD
DD
TSEC3_RX_ER/FEC_RX_ER/ Receive Error
FIFO3_RX_ER
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
107
FREESCALE [ Freescale ]
