Package Description
Table 75. MPC8572E Pinout Listing (continued)
Power
Supply
Signal
Signal Name
Package Pin Number Pin Type
Notes
D2_MRAS
Row Address Strobe
Clock Enable
Chip Select
AA1
O
O
O
O
GV
GV
GV
GV
—
11
—
—
DD
DD
DD
DD
D2_MCKE[0:3]
D2_MCS[0:3]
D2_MCK[0:5]
L3, L1, K1, K2
AB1, AG2, AC1, AH2
Clock
V4, F7, AJ3, V2, E7,
AG4
D2_MCK[0:5]
Clock Complements
V1, F8, AJ4, U1, E6,
AG5
O
GV
—
DD
D2_MODT[0:3]
D2_MDIC[0:1]
On Die Termination
AE1, AG1, AE2, AH1
F1, G1
O
GV
GV
—
DD
DD
Driver Impedance Calibration
I/O
25
Local Bus Controller Interface
LAD[0:31]
Muxed Data/Address
M22, L22, F22, G22,
F21, G21, E20, H22,
K22, K21, H19, J20,
J19, L20, M20, M19,
E22, E21, L19, K19,
G19, H18, E18, G18,
J17, K17, K14, J15,
H16, J14, H15, G15
I/O
BV
34
DD
LDP[0:3]
LA[27]
Data Parity
M21, D22, A24, E17
J21
I/O
O
BV
BV
BV
BV
—
5, 9
DD
DD
DD
DD
Burst Address
Port Address
Chip Selects
LA[28:31]
LCS[0:4]
F20, K18, H20, G17
O
5, 7, 9
10
B23, E16, D20, B25,
A22
O
LCS[5]/DMA2_DREQ[1]
LCS[6]/DMA2_DACK[1]
LCS[7]/DMA2_DDONE[1]
LWE[0]/LBS[0]/LFWE
LWE[1]/LBS[1]
Chip Selects / DMA Request
Chip Selects / DMA Ack
Chip Selects / DMA Done
Write Enable / Byte Select
Write Enable / Byte Select
Write Enable / Byte Select
Write Enable / Byte Select
Address Latch Enable
D19
E19
C21
D17
F15
B24
D18
F19
L18
I/O
O
O
O
O
O
O
O
O
O
BV
BV
BV
BV
BV
BV
BV
BV
BV
BV
1, 10
1, 10
1, 10
5, 9
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
5, 9
LWE[2]/LBS[2]
5, 9
LWE[3]/LBS[3]
5, 9
LALE
5, 8, 9
5, 8, 9
5, 9
LBCTL
Buffer Control
LGPL0/LFCLE
UPM General Purpose Line 0 / J13
Flash Command Latch Enable
LGPL1/LFALE
UPM General Purpose Line 1/ J16
Flash Address Latch Enable
O
BV
5, 9
DD
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
104
FREESCALE [ Freescale ]
