Package Description
Table 75. MPC8572E Pinout Listing (continued)
Power
Supply
Signal
Signal Name
Package Pin Number Pin Type
Notes
SD2_TX[0]
SGMII Tx Data eTSEC1
AD26
O
O
O
I
XV
—
DD_SR
DS2
SD2_TX[3:0]
SD2_PLL_TPD
SD2_REF_CLK
SD2_REF_CLK
Reserved
Transmit Data (negative)
PLL Test Point Digital
PLL Reference Clock
AH27, AG25, AE25,
AD27
XV
—
17
—
—
28
DD_SR
DS2
AH32
XV
DD_SR
DS2
AG32
XV
DD_SR
DS2
PLL Reference Clock
Complement
AG31
I
XV
DD_SR
DS2
—
AF26, AF27
—
—
General-Purpose Input/Output
GPINOUT[0:7]
General Purpose Input / Output B27, A28, B31, A32,
B30, A31, B28, B29
I/O
BV
—
DD
System Control
HRESET
Hard Reset
AC31
L23
I
O
I
OV
OV
OV
OV
OV
OV
OV
—
21
DD
DD
DD
DD
DD
DD
DD
HRESET_REQ
SRESET
Hard Reset Request
Soft Reset
P24
N26
N25
U29
T25
—
CKSTP_IN0
CKSTP_IN1
CKSTP_OUT0
CKSTP_OUT1
Checkstop In Processor 0
Checkstop In Processor 1
Checkstop Out Processor 0
Checkstop Out Processor 1
I
—
I
—
O
O
2, 4
2, 4
Debug
TRIG_IN
Trigger In
P26
I
OV
OV
—
DD
DD
TRIG_OUT/READY_P0/QUIES Trigger Out / Ready Processor P25
O
21
CE
0/ Quiesce
READY_P1
MSRCID[0:1]
MSRCID[2:4]
MDVAL
Ready Processor 1
N28
O
O
O
O
O
OV
OV
OV
OV
OV
5, 9
5, 9, 30
21
DD
DD
DD
DD
DD
Memory Debug Source Port ID U27, T29
Memory Debug Source Port ID U28, W24, W28
Memory Debug Data Valid
Clock Out
V26
U32
2, 21
11
CLK_OUT
Clock
RTC
Real Time Clock
System Clock
V25
Y32
I
I
OV
OV
—
—
DD
DD
SYSCLK
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
110
FREESCALE [ Freescale ]
