Package Description
Table 75. MPC8572E Pinout Listing (continued)
Signal Name Package Pin Number Pin Type
Trigger Out
Power
Supply
Signal
Notes
TSEC_1588_TRIG_OUT
TSEC_1588_CLK_OUT
TSEC_1588_PULSE_OUT1
TSEC_1588_PULSE_OUT2
AA23
AC23
AA22
AB23
O
O
O
O
LV
LV
LV
LV
5, 9
5, 9
5, 9
5, 9
DD
DD
DD
DD
Clock Out
Pulse Out1
Pulse Out2
Ethernet Management Interface 1
EC1_MDC
EC1_MDIO
Management Data Clock
Management Data In/Out
AL30
O
LV
LV
5, 9
—
DD
DD
AM25
I/O
Ethernet Management Interface 3
EC3_MDC
EC3_MDIO
Management Data Clock
Management Data In/Out
AF19
AF18
O
TV
TV
5, 9
—
DD
DD
I/O
Ethernet Management Interface 5
EC5_MDC
EC5_MDIO
Management Data Clock
Management Data In/Out
AF14
AF15
O
TV
TV
21
—
DD
DD
I/O
Gigabit Ethernet Reference Clock
EC_GTX_CLK125
Reference Clock
AM24
I
I
LV
LV
LV
32
1
DD
DD
DD
Three-Speed Ethernet Controller 1
TSEC1_RXD[7:0]/FIFO1_RXD[ Receive Data
7:0]
AM28, AL28, AM26,
AK23, AM27, AK26,
AL29, AM30
TSEC1_TXD[7:0]/FIFO1_TXD[ Transmit Data
7:0]
AC20, AD20, AE22,
AB22, AC22, AD21,
AB21, AE21
O
1, 5, 9
TSEC1_COL/FIFO1_TX_FC
TSEC1_CRS/FIFO1_RX_FC
TSEC1_GTX_CLK
Collision Detect/Flow Control
AJ23
AM31
AK27
AL25
I
I/O
O
I
LV
LV
LV
LV
1
DD
DD
DD
DD
Carrier Sense/Flow Control
Transmit Clock Out
1, 16
TSEC1_RX_CLK/FIFO1_RX_C Receive Clock
LK
1
1
1
1
TSEC1_RX_DV/FIFO1_RX_DV Receive Data Valid
/FIFO1_RXC[0]
AL24
AM29
AB20
I
I
I
LV
LV
LV
DD
DD
DD
TSEC1_RX_ER/FIFO1_RX_E Receive Data Error
R/FIFO1_RXC[1]
TSEC1_TX_CLK/FIFO1_TX_C Transmit Clock In
LK
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
106
FREESCALE [ Freescale ]
