Package Description
Table 75. MPC8572E Pinout Listing (continued)
Signal Name Package Pin Number Pin Type
Power
Supply
Signal
Notes
TSEC3_TX_CLK/FEC_TX_CL Transmit Clock In
K/FIFO3_TX_CLK
AF16
AJ18
I
TV
TV
1
DD
DD
TSEC3_TX_EN/FEC_TX_EN/F Transmit Enable
IFO3_TX_EN
O
1, 22
Three-Speed Ethernet Controller 4
TSEC4_TXD[3:0]/TSEC3_TXD[ Transmit Data AD15, AC16, AC14,
O
I
TV
TV
1, 5, 9
1
DD
DD
7:4]/FIFO3_TXD[7:4]
AB16
TSEC4_RXD[3:0]/TSEC3_RXD Receive Data
[7:4]/FIFO3_RXD[7:4]
AE15, AF13, AE14,
AH14
TSEC4_GTX_CLK
Transmit Clock Out
AB14
AG13
O
I
TV
TV
—
1
DD
DD
TSEC4_RX_CLK/TSEC3_COL/ Receive Clock
FEC_COL/FIFO3_TX_FC
TSEC4_RX_DV/TSEC3_CRS/ Receive Data Valid
FEC_CRS/FIFO3_RX_FC
AD13
AB15
I/O
O
TV
TV
1, 23
1, 22
DD
DD
TSEC4_TX_EN/TSEC3_TX_E Transmit Enable
R/FEC_TX_ER/FIFO3_TX_ER
DUART
UART_CTS[0:1]
UART_RTS[0:1]
UART_SIN[0:1]
UART_SOUT[0:1]
Clear to Send
Ready to Send
Receive Data
Transmit Data
W30, Y27
W31, Y30
Y26, W29
Y25, W26
I
OV
OV
OV
OV
—
5, 9
—
DD
DD
DD
DD
O
I
O
5, 9
2
I C Interface
IIC1_SCL
IIC1_SDA
IIC2_SCL
IIC2_SDA
Serial Clock
Serial Data
Serial Clock
Serial Data
AC30
I/O
I/O
I/O
I/O
OV
OV
OV
OV
4, 20
4, 20
4, 20
4, 20
DD
DD
DD
DD
AB30
AD30
AD29
SerDes (x10) PCIe, SRIO
SD1_RX[7:0]
SD1_RX[7:0]
SD1_TX[7]
Receive Data (positive)
Receive Data (negative)
P32, N30, M32, L30,
G30, F32, E30, D32
I
I
XV
—
—
—
DD_SR
DS1
P31, N29, M31, L29,
G29, F31, E29, D31
XV
DD_SR
DS1
PCIe1 Tx Data Lane 7 / SRIO or M26
PCIe2 Tx Data Lane 3 / PCIe3
TX Data Lane 1
O
XV
DD_SR
DS1
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
108
FREESCALE [ Freescale ]
