Package Description
Table 75. MPC8572E Pinout Listing (continued)
Signal Name Package Pin Number Pin Type
Clock Enable
Power
Notes
Signal
D1_MCKE[0:3]
Supply
M8, L9, T9, N8
O
O
GV
GV
11
—
DD
DD
D1_MCS[0:3]
D1_MCK[0:5]
D1_MCK[0:5]
D1_MODT[0:3]
D1_MDIC[0:1]
Chip Select
AB9, AF10, AB11,
AE11
Clock
V7, E13, AH11, Y9,
F14, AG10
O
O
GV
GV
GV
GV
—
—
—
25
DD
DD
DD
DD
Clock Complements
On Die Termination
Driver Impedance Calibration
Y10, E12, AH12, AA11,
F13, AG11
AD10, AF12, AC10,
AE12
O
E15, G14
I/O
DDR SDRAM Memory Interface 2
D2_MDQ[0:63]
Data
A6, B7, C5, D5, A7, C8,
D8, D6, C4, A3, D3,
D2, B4, A4, B1, C1, E3,
E1, G2, G6, D1, E4,
G5, G3, J4, J2, P4, R5,
H3, H1, N5, N3, Y6, Y4,
AC3, AD2, V5, W5,
AB2, AB3, AD5, AE3,
AF6, AG7, AC4, AD4,
AF4, AF7, AH5, AJ1,
AL2, AM3, AH3, AH6,
AM1, AL3, AK5, AL5,
AJ7, AK7, AK4, AM4,
AL6, AM7
I/O
GV
—
DD
D2_MECC[0:7]
Error Correcting Code
J5, H7, L7, N6, H4, H6,
M4, M5
I/O
GV
—
DD
D2_MAPAR_ERR
D2_MAPAR_OUT
D2_MDM[0:8]
Address Parity Error
Address Parity Out
Data Mask
N1
I
GV
GV
GV
—
—
—
DD
DD
DD
W2
O
O
A5, B3, F4, J1, AA4,
AE5, AK1, AM5, K5
D2_MDQS[0:8]
D2_MDQS[0:8]
D2_MA[0:15]
Data Strobe
Data Strobe
Address
B6, C2, F5, L4, AB5,
AF3, AL1, AM6, L6
I/O
I/O
O
GV
GV
GV
—
—
—
DD
DD
DD
C7, A2, F2, K3, AA5,
AE6, AK2, AJ6, K6
W1, U4, U3, T1, T2, T3,
R1, R2, T5, R4, Y3, P1,
N2, AF1, M2, M1
D2_MBA[0:2]
D2_MWE
Bank Select
Y1, W3, P3
AA2
O
O
O
GV
GV
GV
—
—
—
DD
DD
DD
Write Enable
D2_MCAS
Column Address Strobe
AD1
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
103
FREESCALE [ Freescale ]
