Package Description
Table 75. MPC8572E Pinout Listing (continued)
Power
Notes
Signal
Signal Name
Package Pin Number Pin Type
Supply
SD1_TX[6]
PCIe1 Tx Data Lane 6 / SRIO or L24
PCIe2 Tx Data Lane 2 / PCIe3
TX Data Lane 0
O
XV
—
DD_SR
DS1
SD1_TX[5]
SD1_TX[4]
SD1_TX[3]
SD1_TX[2]
SD1_TX[1]
SD1_TX[0]
PCIe1 Tx Data Lane 5 / SRIO or K26
PCIe2 Tx Data Lane 1
O
O
O
O
O
O
O
O
I
XV
—
—
—
—
—
—
—
17
—
—
DD_SR
DS1
PCIe1 Tx Data Lane 4 / SRIO or J24
PCIe2 Tx Data Lane 0
XV
DD_SR
DS1
PCIe1 Tx Data Lane 3
PCIe1 Tx Data Lane 2
PCIe1 Tx Data Lane 1]
PCIe1 Tx Data Lane 0
Transmit Data (negative)
PLL Test Point Digital
PLL Reference Clock
G24
F26
E24
D26
XV
DD_SR
DS1
XV
DD_SR
DS1
XV
DD_SR
DS1
XV
DD_SR
DS1
SD1_TX[7:0]
M27, L25, K27, J25,
G25, F27, E25, D27
XV
DD_SR
DS1
SD1_PLL_TPD
SD1_REF_CLK
SD1_REF_CLK
J32
H32
H31
XV
DD_SR
DS1
XV
DD_SR
DS1
PLL Reference Clock
Complement
I
XV
DD_SR
DS1
Reserved
Reserved
Reserved
Reserved
—
—
—
—
C29, K32
—
—
—
—
—
—
—
—
26
27
28
29
C30, K31
C24, C25, H26, H27
AL20, AL21
SerDes (x4) SGMII
SD2_RX[3:0]
SD2_RX[3:0]
SD2_TX[3]
SD2_TX[2]
SD2_TX[1]
Receive Data (positive)
Receive Data (negative)
SGMII Tx Data eTSEC4
SGMII Tx Data eTSEC3
SGMII Tx Data eTSEC2
AK32, AJ30, AF30,
AE32
I
XV
—
—
—
—
—
DD_SR
DS2
AK31, AJ29, AF29,
AE31
I
XV
DD_SR
DS2
AH26
AG24
AE24
O
O
O
XV
DD_SR
DS2
XV
DD_SR
DS2
XV
DD_SR
DS2
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
109
FREESCALE [ Freescale ]
