Ethernet: Three-Speed,10/100, MII Management
8.4.2 MII Management AC Electrical Specifications
provides the MII management AC timing specifications.
Table 34. MII Management AC Timing Specifications
At recommended operating conditions with OV
DD
is 3.3 V ± 5%.
Parameter/Condition
MDC frequency
MDC period
MDC clock pulse width high
MDC to MDIO valid
MDC to MDIO delay
MDIO to MDC setup time
MDIO to MDC hold time
MDC rise time
MDC fall time
Symbol
1
f
MDC
t
MDC
t
MDCH
t
MDKHDV
t
MDKHDX
t
MDDVKH
t
MDDXKH
t
MDCR
t
MDHF
Min
0.893
96
32
Typ
—
—
—
Max
10.4
1120
—
2*[1/(f
ccb_clk
/8)]
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Notes
2, 4
3
3
10
5
0
—
—
—
—
—
—
—
2*[1/(f
ccb_clk
/8)]
—
—
10
10
4
4
Notes:
1.The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
(reference)(state)
for inputs and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
MDKHDX
symbolizes management data timing (MD) for the time t
MDC
from clock reference (K) high (H) until data outputs (D) are
invalid (X) or data hold time. Also, t
MDDVKH
symbolizes management data timing (MD) with respect to the time data
input signals (D) reach the valid state (V) relative to the t
MDC
clock reference (K) going to the high (H) state or setup
time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2.This parameter is dependent on the CCB clock speed (that is, for a CCB clock of 267 MHz, the maximum frequency is
8.3 MHz and the minimum frequency is 1.2 MHz; for a CCB clock of 333 MHz, the maximum frequency is 10.4 MHz
and the minimum frequency is 1.5 MHz).
3.This parameter is dependent on the CCB clock speed (that is, for a CCB clock of 267 MHz, the delay is 60 ns and for a
CCB clock of 333 MHz, the delay is 48 ns).
4.Guaranteed by design.
shows the MII management AC timing diagram.
t
MDC
MDC
t
MDCH
MDIO
(Input)
t
MDDVKH
t
MDKHDV
MDIO
(Output)
t
MDKHDX
t
MDDXKH
t
MDCF
t
MDCR
Figure 16. MII Management Interface Timing Diagram
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
35
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
