Local Bus
Table 37. Local Bus General Timing Parameters—DLL Bypassed (continued)
Parameter
Local bus clock to output high impedance
for LAD/LDP
POR Configuration
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
(default)
Symbol
1
t
LBKLOZ2
Min
—
Max
0.2
1.5
Unit
ns
Notes
7
Notes:
1.The symbols used for timing specifications herein follow the pattern of t
(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
(First two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
LBIXKH1
symbolizes local
bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t
LBK
clock reference (K) goes high (H), in this
case for clock one(1). Also, t
LBKHOX
symbolizes local bus timing (LB) for the t
LBK
clock reference (K) to go high (H), with
respect to the output (O) going invalid (X) or output hold time.
2.All timings are in reference to local bus clock for DLL bypass mode. Timings may be negative with respect to the local bus
clock because the actual launch and capture of signals is done with the internal launch/capture clock, which precedes
LCLK by t
LBKHKT
.
3.Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at OV
DD
/2.
4.All signals are measured from OV
DD
/2 of the rising edge of local bus clock for DLL bypass mode to 0.4
×
OV
DD
of the signal
in question for 3.3-V signaling levels.
5.Input timings are measured at the pin.
6.The value of t
LBOTOT
is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number of local
bus buffer delays used as programmed at power-on reset with configuration pins TSEC2_TXD[6:5].
7.For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
8.Guaranteed by characterization.
9.Guaranteed by design.
provides the AC test load for the local bus.
Output
Z
0
= 50
Ω
R
L
= 50
Ω
OV
DD
/2
Figure 17. Local Bus AC Test Load
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
39
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
