Local Bus
describes the general timing parameters of the local bus interface of the MPC8540 with the DLL
bypassed.
Table 37. Local Bus General Timing Parameters—DLL Bypassed
Parameter
Local bus cycle time
Internal launch/capture clock to LCLK
delay
LCLK[n] skew to LCLK[m] or LSYNC_OUT
Input setup to local bus clock (except
LUPWAIT)
LUPWAIT input setup to local bus clock
Input hold from local bus clock (except
LUPWAIT)
LUPWAIT input hold from local bus clock
LALE output transition to LAD/LDP output
transition (LATCH hold time)
Local bus clock to output valid (except
LAD/LDP and LALE)
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
(default)
Local bus clock to data valid for LAD/LDP
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
(default)
Local bus clock to address valid for LAD
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
(default)
Local bus clock to LALE assertion
Output hold from local bus clock (except
LAD/LDP and LALE)
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
(default)
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
(default)
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
(default)
t
LBKLOZ1
t
LBKLOX2
t
LBKHOV4
t
LBKLOX1
—
-3.2
-2.3
-3.2
-2.3
—
0.2
1.5
ns
7
—
ns
4
t
LBKLOV3
—
t
LBKLOV2
—
POR Configuration
Symbol
1
t
LBK
t
LBKHKT
t
LBKSKEW
t
LBIVKH1
t
LBIVKH2
t
LBIXKH1
t
LBIXKH2
t
LBOTOT
t
LBKLOV1
Min
6.0
2.3
—
5.7
5.6
-1.8
-1.3
1.5
—
Max
—
3.9
150
—
—
—
—
—
-0.3
1.2
-0.1
1.4
0
1.5
0
—
ns
ns
4
4
ns
4
ns
4
Unit
ns
ns
ps
ns
ns
ns
ns
ns
ns
Notes
2
8
3, 9
4, 5
4, 5
4, 5
4, 5
6
4
Output hold from local bus clock for
LAD/LDP
Local bus clock to output high Impedance
(except LAD/LDP and LALE)
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
38
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
