Ethernet: Three-Speed,10/100, MII Management
Figure 14 shows the MII transmit AC timing diagram.
tMTXR
tMTX
TX_CLK
tMTXF
tMTXH
TXD[3:0]
TX_EN
TX_ER
tMTKHDX
Figure 14. MII Transmit AC Timing Diagram
8.3.2.2 MII Receive AC Timing Specifications
Table 32 provides the MII receive AC timing specifications.
Table 32. MII Receive AC Timing Specifications
Parameter/Condition
RX_CLK clock period 10 Mbps
Symbol 1
Min
Typ
Max
Unit
tMRX
tMRX
tMRXH/ MRX
tMRDVKH
tMRDXKH
—
—
400
40
—
—
—
ns
ns
%
RX_CLK clock period 100 Mbps
RX_CLK duty cycle
t
35
65
—
RXD[7:0], TX_DV, TX_ER setup time to RX_CLK
RXD[7:0], TX_DV, TX_ER hold time to RX_CLK
RX_CLK clock rise and fall time
Note:
10.0
10.0
1.0
—
ns
ns
ns
—
—
2,3
tMRXR, tMRXF
—
4.0
1.The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH
symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to
the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKH symbolizes MII receive timing
(GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to
the high (H) state or hold time. Note that, in general, the clock reference symbol representation is based on two to
three letters representing the clock of a particular functional. For example, the subscript of tMRX represents the MII
(M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F
(fall).
2.Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3.Guaranteed by design.
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
33
FREESCALE [ Freescale ]
