Local Bus
Table 36. Local Bus General Timing Parameters - DLL Enabled (continued)
Parameter
Local bus clock to output valid
(except LAD/LDP and LALE)
POR Configuration
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
(default)
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
(default)
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
(default)
t
LBKHOV4
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
(default)
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
(default)
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
(default)
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
(default)
t
LBKHOZ2
—
t
LBKHOZ1
t
LBKHOX2
t
LBKHOX1
—
0.7
1.6
0.7
1.6
—
2.5
3.8
2.5
3.8
ns
7, 9
ns
7, 9
—
ns
4, 8
t
LBKHOV3
—
t
LBKHOV2
—
Symbol
1
t
LBKHOV1
Min
—
Max
2.0
3.5
2.2
3.7
2.3
3.8
2.3
—
ns
ns
4, 8
4, 8
ns
4, 8
ns
4, 8
Unit
ns
Notes
4, 8
Local bus clock to data valid for
LAD/LDP
Local bus clock to address valid for
LAD
Local bus clock to LALE assertion
Output hold from local bus clock
(except LAD/LDP and LALE)
Output hold from local bus clock for
LAD/LDP
Local bus clock to output high
Impedance (except LAD/LDP and
LALE)
Local bus clock to output high
impedance for LAD/LDP
Notes:
1.The symbols used for timing specifications herein follow the pattern of t
(First two letters of functional block)(signal)(state)
(reference)(state)
for inputs and t
(First two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example,
t
LBIXKH1
symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t
LBK
clock
reference (K) goes high (H), in this case for clock one(1). Also, t
LBKHOX
symbolizes local bus timing (LB) for the t
LBK
clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time.
2.All timings are in reference to LSYNC_IN for DLL enabled mode.
3.Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at OV
DD
/2.
4.All signals are measured from OV
DD
/2 of the rising edge of LSYNC_IN for DLL enabled to 0.4
×
OV
DD
of the signal in
question for 3.3-V signaling levels.
5.Input timings are measured at the pin.
6.The value of t
LBOTOT
is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number
of local bus buffer delays used as programmed at power-on reset with configuration pins TSEC2_TXD[6:5].
7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
8.Guaranteed by characterization.
9.Guaranteed by design.
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
37
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
