DDR SDRAM
MDQS[n]
MDQ[n]
t
DISKEW
t
DISKEW
Figure 3. DDR SDRAM Interface Input Timing
6.2.2 DDR SDRAM Output AC Timing Specifications
For chip selects MCS1 and MCS2, there will always be at least 200 DDR memory clocks coming out of
self-refresh after an HRESET before a precharge occurs. This will not necessarily be the case for chip
selects MCS0 and MCS3.
6.2.2.1
DLL Enabled Mode
and
provide the output AC timing specifications and measurement conditions for the
DDR SDRAM interface with the DDR DLL enabled.
Table 16. DDR SDRAM Output AC Timing Specifications–DLL Mode
At recommended operating conditions with GV
DD
of 2.5 V ± 5%.
Parameter
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)
On chip Clock Skew
MCK[n] duty cycle
ADDR/CMD output valid
ADDR/CMD output invalid
Write CMD to first MDQS capture edge
MDQ/MECC/MDM output setup with respect to
MDQS
333 MHz
266 MHz
200 MHz
MDQ/MECC/MDM output hold with respect to
MDQS
333 MHz
266 MHz
200 MHz
MDQS preamble start
Symbol
1
t
MCK
t
MCKSKEW
t
MCKH
/t
MCK
t
DDKHOV
t
DDKHOX
t
DDSHMH
t
DDKHDS,
t
DDKLDS
Min
6
—
45
—
1
t
MCK
+ 1.5
Max
10
150
55
3
—
t
MCK
+ 4.0
—
Unit
ns
ps
%
ns
ns
ns
ps
Notes
2
3, 8
8
4, 9
4, 9
5
6, 9
900
1100
1200
t
DDKHDX,
t
DDKLDX
900
1100
1200
t
DDSHMP
0.75
×
t
MCK
+ 1.5
0.75
×
t
MCK
+ 4.0
ns
7, 8
—
ps
6, 9
MPC8540 Integrated Processor Hardware Specifications, Rev. 4
18
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
