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MPC8347ECVVAGDB 参数 Datasheet PDF下载

MPC8347ECVVAGDB图片预览
型号: MPC8347ECVVAGDB
PDF下载: 下载PDF文件 查看货源
内容描述: MPC8347EA的PowerQUICC II Pro整合型主机处理器的硬件规格 [MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications]
分类和应用: 外围集成电路PC时钟
文件页数/大小: 99 页 / 727 K
品牌: FREESCALE [ Freescale ]
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DDR and DDR2 SDRAM  
Table 12. DDR2 SDRAM DC Electrical Characteristics for GV (typ) = 1.8 V (continued)  
DD  
Output low current (VOUT = 0.280 V)  
IOL  
13.4  
mA  
Notes:  
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.  
2. MVREF is expected to equal 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise  
on MVREF cannot exceed 2% of the DC value.  
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to equal  
MVREF. This rail should track variations in the DC level of MVREF  
.
4. Output leakage is measured with all outputs disabled, 0 V VOUT GVDD  
.
Table 13 provides the DDR2 capacitance when GVDD(typ) = 1.8 V.  
Table 13. DDR2 SDRAM Capacitance for GV (typ) = 1.8 V  
DD  
Parameter/Condition  
Symbol  
Min  
Max  
Unit  
Notes  
Input/output capacitance: DQ, DQS, DQS  
Delta input/output capacitance: DQ, DQS, DQS  
Note:  
CIO  
6
8
pF  
pF  
1
1
CDIO  
0.5  
1. This parameter is sampled. GVDD = 1.8 V 0.090 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.  
Table 14 provides the recommended operating conditions for the DDR SDRAM component(s) when  
GV (typ) = 2.5 V.  
DD  
Table 14. DDR SDRAM DC Electrical Characteristics for GV (typ) = 2.5 V  
DD  
Parameter/Condition  
I/O supply voltage  
Symbol  
Min  
Max  
Unit  
Notes  
GVDD  
MVREF  
VTT  
2.375  
0.49 × GVDD  
MVREF – 0.04  
MVREF + 0.18  
–0.3  
2.625  
0.51 × GVDD  
MVREF + 0.04  
GVDD + 0.3  
MVREF – 0.18  
–9.9  
V
V
1
2
I/O reference voltage  
I/O termination voltage  
Input high voltage  
V
3
VIH  
V
4
Input low voltage  
VIL  
V
Output leakage current  
Output high current (VOUT = 1.95 V)  
Output low current (VOUT = 0.35 V)  
Notes:  
IOZ  
–9.9  
μA  
mA  
mA  
IOH  
–15.2  
IOL  
15.2  
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.  
2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak  
noise on MVREF may not exceed 2% of the DC value.  
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be  
equal to MVREF. This rail should track variations in the DC level of MVREF  
.
4. Output leakage is measured with all outputs disabled, 0 V VOUT GVDD  
.
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12  
Freescale Semiconductor  
17