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MPC8347ECVVAGDB 参数 Datasheet PDF下载

MPC8347ECVVAGDB图片预览
型号: MPC8347ECVVAGDB
PDF下载: 下载PDF文件 查看货源
内容描述: MPC8347EA的PowerQUICC II Pro整合型主机处理器的硬件规格 [MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications]
分类和应用: 外围集成电路PC时钟
文件页数/大小: 99 页 / 727 K
品牌: FREESCALE [ Freescale ]
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RESET Initialization  
1
Table 9. RESET Pins DC Electrical Characteristics (continued)  
Parameter  
Symbol  
Condition  
Min  
Max  
0.4  
Unit  
Output low voltage  
V
IOL = 3.2 mA  
V
OL  
Notes:  
1. This table applies for pins PORESET, HRESET, SRESET, and QUIESCE.  
2. HRESET and SRESET are open drain pins, thus VOH is not relevant for those pins.  
5.2  
RESET AC Electrical Characteristics  
Table 10 provides the reset initialization AC timing specifications of the MPC8347EA.  
Table 10. RESET Initialization Timing Specifications  
Parameter  
Min  
Max  
Unit  
Notes  
Required assertion time of HRESET or SRESET (input) to activate reset flow  
32  
32  
tPCI_SYNC_IN  
tCLKIN  
1
2
Required assertion time of PORESET with stable clock applied to CLKIN when the  
MPC8347EA is in PCI host mode  
Required assertion time of PORESET with stable clock applied to PCI_SYNC_IN  
when the MPC8347EA is in PCI agent mode  
32  
tPCI_SYNC_IN  
1
HRESET/SRESET assertion (output)  
512  
16  
4
tPCI_SYNC_IN  
tPCI_SYNC_IN  
tCLKIN  
1
1
2
HRESET negation to SRESET negation (output)  
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and  
CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8347EA is  
in PCI host mode  
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and  
CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8347EA is  
in PCI agent mode  
4
tPCI_SYNC_IN  
1
Input hold time for POR configuration signals with respect to negation of HRESET  
0
4
ns  
ns  
3
Time for the MPC8347EA to turn off POR configuration signals with respect to the  
assertion of HRESET  
Time for the MPC8347EA to turn on POR configuration signals with respect to the  
negation of HRESET  
1
tPCI_SYNC_IN 1, 3  
Notes:  
1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. In PCI host mode, the primary clock is applied  
to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the MPC8349EA  
PowerQUICC II Pro Integrated Host Processor Family Reference Manual.  
2. tCLKIN is the clock period of the input clock applied to CLKIN. It is valid only in PCI host mode. See the MPC8349EA  
PowerQUICC II Pro Integrated Host Processor Family Reference Manual.  
3. POR configuration signals consist of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.  
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12  
Freescale Semiconductor  
15