DDR and DDR2 SDRAM
Table 19 provides the input AC timing specifications for the DDR SDRAM interface.
Table 19. DDR and DDR2 SDRAM Input AC Timing Specifications
At recommended operating conditions with GVDD of (1.8 or 2.5 V) 5%.
Parameter
Symbol
Min
Max
Unit
Notes
Controller Skew for MDQS—MDQ/MECC/MDM
tCISKEW
ps
1, 2
3
400 MHz
–600
–750
–750
–750
600
750
750
750
333 MHz
266 MHz
200 MHz
—
—
—
Notes:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
will be captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be
determined by the equation: tDISKEW
value of tCISKEW
=
(T/4 – abs (tCISKEW)); where T is the clock period and abs (tCISKEW) is the absolute
.
3. This specification applies only to the DDR interface.
Figure 5 illustrates the DDR input timing diagram showing the t
timing parameter.
DISKEW
MCK[n]
MCK[n]
tMCK
MDQS[n]
MDQ[x]
D0
D1
tDISKEW
tDISKEW
Figure 5. DDR Input Timing Diagram
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
Freescale Semiconductor
19
FREESCALE [ Freescale ]
