DDR and DDR2 SDRAM
6.2.2
DDR and DDR2 SDRAM Output AC Timing Specifications
Table 20 shows the DDR and DDR2 output AC timing specifications.
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications
At recommended operating conditions with GVDD of (1.8 or 2.5 V) 5%.
Parameter
Symbol 1
Min
Max
Unit
Notes
MCK[n] cycle time, (MCK[n]/MCK[n] crossing) (PBGA
package)
tMCK
5
—
ns
2
MCK[n] cycle time, (MCK[n]/MCK[n] crossing) (TBGA
package)
tMCK
7.5
—
ns
ns
2
3
ADDR/CMD/MODT output setup with respect to MCK
tDDKHAS
400 MHz
1.95
2.40
3.15
4.20
—
—
—
—
333 MHz
266 MHz
200 MHz
ADDR/CMD/MODT output hold with respect to MCK
tDDKHAX
tDDKHCS
tDDKHCX
tDDKHMH
ns
ns
ns
3
3
3
400 MHz
1.95
2.40
3.15
4.20
—
—
—
—
333 MHz
266 MHz
200 MHz
MCS(n) output setup with respect to MCK
400 MHz
1.95
2.40
3.15
4.20
—
—
—
—
333 MHz
266 MHz
200 MHz
MCS(n) output hold with respect to MCK
400 MHz
1.95
2.40
3.15
4.20
–0.6
—
—
333 MHz
266 MHz
—
200 MHz
—
MCK to MDQS Skew
0.6
ns
ps
4
5
MDQ/MECC/MDM output setup with respect to
MDQS
tDDKHDS,
tDDKLDS
400 MHz
700
775
—
—
—
—
333 MHz
266 MHz
1100
1200
200 MHz
MDQ/MECC/MDM output hold with respect to MDQS
tDDKHDX,
tDDKLDX
ps
5
400 MHz
333 MHz
700
900
—
—
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
Freescale Semiconductor
20
FREESCALE [ Freescale ]
