DDR and DDR2 SDRAM
Table 11 lists the PLL and DLL lock times.
Table 11. PLL and DLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times
DLL lock times
Notes:
—
100
μs
—
7680
122,880
csb_clk cycles
1, 2
1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio
results in the minimum and an 8:1 ratio results in the maximum.
2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 19, “Clocking.”
6 DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8347EA. Note that DDR SDRAM is GV (typ) = 2.5 V and DDR2 SDRAM is GV (typ) = 1.8 V.
DD
DD
The AC electrical specifications are the same for DDR and DRR2 SDRAM.
NOTE
The information in this document is accurate for revision 3.0 silicon and
later. For information on revision 1.1 silicon and earlier versions see the
MPC8347E PowerQUICC II Pro Integrated Host Processor Hardware
Specifications. See Section 22.1, “Part Numbers Fully Addressed by This
Document,” for silicon revision level determination.
6.1
DDR and DDR2 SDRAM DC Electrical Characteristics
Table 12 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the
MPC8347EA when GV (typ) = 1.8 V.
DD
Table 12. DDR2 SDRAM DC Electrical Characteristics for GV (typ) = 1.8 V
DD
Parameter/Condition
I/O supply voltage
Symbol
Min
Max
Unit
Notes
GVDD
MVREF
VTT
1.71
0.49 × GVDD
MVREF – 0.04
MVREF + 0.125
–0.3
1.89
0.51 × GVDD
MVREF + 0.04
GVDD + 0.3
MVREF – 0.125
9.9
V
V
1
2
I/O reference voltage
I/O termination voltage
Input high voltage
V
3
VIH
V
—
—
4
Input low voltage
VIL
V
Output leakage current
Output high current (VOUT = 1.420 V)
IOZ
–9.9
μA
mA
IOH
–13.4
—
—
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
Freescale Semiconductor
16
FREESCALE [ Freescale ]
