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MPC8347ECVVAGDB 参数 Datasheet PDF下载

MPC8347ECVVAGDB图片预览
型号: MPC8347ECVVAGDB
PDF下载: 下载PDF文件 查看货源
内容描述: MPC8347EA的PowerQUICC II Pro整合型主机处理器的硬件规格 [MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications]
分类和应用: 外围集成电路PC时钟
文件页数/大小: 99 页 / 727 K
品牌: FREESCALE [ Freescale ]
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Clock Input Timing  
4 Clock Input Timing  
This section provides the clock input DC and AC electrical characteristics for the device.  
4.1  
DC Electrical Characteristics  
Table 6 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the MPC8347EA.  
Table 6. CLKIN DC Timing Specifications  
Parameter  
Input high voltage  
Condition  
Symbol  
Min  
Max  
Unit  
VIH  
VIL  
IIN  
2.7  
–0.3  
OVDD + 0.3  
V
V
Input low voltage  
0.4  
10  
10  
CLKIN input current  
PCI_SYNC_IN input current  
0 V VIN OVDD  
μA  
μA  
0 V VIN 0.5 V or  
IIN  
OVDD – 0.5 V VIN OVDD  
PCI_SYNC_IN input current  
0.5 V VIN OVDD – 0.5 V  
IIN  
50  
μA  
4.2  
AC Electrical Characteristics  
The primary clock source for the MPC8347EA can be one of two inputs, CLKIN or PCI_CLK, depending  
on whether the device is configured in PCI host or PCI agent mode. Table 7 provides the clock input  
(CLKIN/PCI_CLK) AC timing specifications for the device.  
Table 7. CLKIN AC Timing Specifications  
Parameter/Condition  
CLKIN/PCI_CLK frequency  
Symbol  
Min  
Typical  
Max  
Unit  
Notes  
fCLKIN  
tCLKIN  
15  
0.6  
40  
66  
MHz  
ns  
1, 6  
2
CLKIN/PCI_CLK cycle time  
CLKIN/PCI_CLK rise and fall time  
CLKIN/PCI_CLK duty cycle  
CLKIN/PCI_CLK jitter  
Notes:  
tKH, tKL  
tKHK/tCLKIN  
1.0  
2.3  
60  
ns  
%
3
150  
ps  
4, 5  
1. Caution: The system, core, USB, security, and TSEC must not exceed their respective maximum or minimum operating  
frequencies.  
2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 and 2.7 V.  
3. Timing is guaranteed by design and characterization.  
4. This represents the total input jitter—short term and long term—and is guaranteed by design.  
5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to  
allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.  
6. Spread spectrum clocking is allowed with 1% input frequency down-spread at maximum 50 KHz modulation rate regardless  
of input frequency.  
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12  
Freescale Semiconductor  
13