RESET Initialization
4.3
TSEC Gigabit Reference Clock Timing
Table 8 provides the TSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications.
Table 8. EC_GTX_CLK125 AC Timing Specifications
At recommended operating conditions with LVDD = 2.5 0.125 mV/ 3.3 V 165 mV
Parameter
Symbol
Min
Typical
Max
Unit
Notes
EC_GTX_CLK125 frequency
EC_GTX_CLK125 cycle time
EC_GTX_CLK125 rise and fall time
tG125
tG125
—
—
—
125
8
—
—
MHz
ns
—
—
1
t
G125R/tG125F
—
ns
LVDD = 2.5 V
LVDD = 3.3 V
0.75
1.0
EC_GTX_CLK125 duty cycle
tG125H/tG125
—
—
%
2
2
GMII, TBI
45
47
55
53
1000Base-T for RGMII, RTBI
EC_GTX_CLK125 jitter
Notes:
—
—
150
ps
1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for LVDD = 2.5 V and from 0.6 and 2.7 V for
LVDD = 3.3 V.
2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. The EC_GTX_CLK125
duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC
GTX_CLK. See Section 8.2.4, “RGMII and RTBI AC Timing Specifications for the duty cycle for 10Base-T and 100Base-T
reference clock.
5 RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the MPC8347EA.
5.1
RESET DC Electrical Characteristics
Table 9 provides the DC electrical characteristics for the RESET pins of the MPC8347EA.
1
Table 9. RESET Pins DC Electrical Characteristics
Parameter
Symbol
Condition
Min
Max
Unit
Input high voltage
Input low voltage
Input current
VIH
VIL
—
—
2.0
–0.3
—
OVDD + 0.3
V
V
0.8
5
IIN
—
μA
V
Output high voltage2
Output low voltage
VOH
VOL
IOH = –8.0 mA
IOL = 8.0 mA
2.4
—
—
0.5
V
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
Freescale Semiconductor
14
FREESCALE [ Freescale ]
