Port Integration Module (S12PPIMV1)
2.3.46 Port P Interrupt Enable Register (PIEP)
Read: Anytime.
Address 0x025E
Access: User read/write(1)
7
6
5
4
3
2
1
0
R
W
0
PIEP7
PIEP5
PIEP4
PIEP3
PIEP2
PIEP1
PIEP0
Reset
0
0
0
0
0
0
0
0
Figure 2-44. Port P Interrupt Enable Register (PIEP)
1. Read: Anytime
Write: Anytime
Table 2-41. PIEP Register Field Descriptions
Description
Field
7,5-0
PIEP
Port P interrupt enable—
This bit enables or disables on the edge sensitive pin interrupt on the associated pin.
1 Interrupt is enabled
0 Interrupt is disabled (interrupt flag masked)
2.3.47 Port P Interrupt Flag Register (PIFP)
Address 0x025F
Access: User read/write(1)
7
6
5
4
3
2
1
0
R
W
0
PIFP7
PIFP5
PIFP4
PIFP3
PIFP2
PIFP1
PIFP0
Reset
0
0
0
0
0
0
0
0
Figure 2-45. Port P Interrupt Flag Register (PIFP)
1. Read: Anytime
Write: Anytime
Table 2-42. PIFP Register Field Descriptions
Description
Field
7,5-0
PIFP
Port P interrupt flag—
The flag bit is set after an active edge was applied to the associated input pin. This can be a rising or a falling edge
based on the state of the polarity select register.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)
0 No active edge occurred
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
91
FREESCALE [ Freescale ]
