Port Integration Module (S12PPIMV1)
2.3.50 Port J Input Register (PTIJ)
Address 0x0269
Access: User read(1)
7
6
5
4
3
2
1
0
R
W
PTIJ7
PTIJ6
0
0
0
PTIJ2
PTIJ1
PTIJ0
Reset
u
u
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-48. Port J Input Register (PTIJ)
1. Read: Anytime
Write:Never, writes to this register have no effect.
Table 2-44. PTIJ Register Field Descriptions
Field
Description
7-6, 2-0 Port J input data—
PTIJ
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
2.3.51 Port J Data Direction Register (DDRJ)
Address 0x026A
Access: User read/write(1)
7
6
5
4
3
2
1
0
R
W
0
0
0
DDRJ7
DDRJ6
DDRJ2
DDRJ1
DDRJ0
Reset
0
0
0
0
0
0
0
0
Figure 2-49. Port J Data Direction Register (DDRJ)
1. Read: Anytime
Write: Anytime
Table 2-45. DDRJ Register Field Descriptions
Description
Field
7-6, 2-0 Port J data direction—
DDRJ This bit determines whether the associated pin is an input or output.
1 Associated pin is configured as output
0 Associated pin is configured as input
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
93
FREESCALE [ Freescale ]
