Port Integration Module (S12PPIMV1)
Table 2-37. DDRP Register Field Descriptions (continued)
Field
Description
5
Port P data direction—
DDRP
This bit determines whether the associated pin is an input or output.
The PWM forces the I/O state to be an output for an enabled channel. If the emergency shut-down feature is enabled
this pin is an input. In this case the data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
4-0
Port P data direction—
DDRP
This bit determines whether the associated pin is an input or output.
The PWM forces the I/O state to be an output for an enabled channel. In this case the data direction bit will not
change.
1 Associated pin is configured as output
0 Associated pin is configured as input
2.3.43 Port P Reduced Drive Register (RDRP)
Address 0x025B
Access: User read/write(1)
7
6
5
4
3
2
1
0
R
W
0
RDRP7
RDRP5
RDRP4
RDRP3
RDRP2
RDRP1
RDRP0
Reset
0
0
0
0
0
0
0
0
Figure 2-41. Port P Reduced Drive Register (RDRP)
1. Read: Anytime
Write: Anytime
Table 2-38. RDRP Register Field Descriptions
Description
Field
7,5-0
Port P reduced drive—Select reduced drive for output pin
RDRP
This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
89
FREESCALE [ Freescale ]
