Port Integration Module (S12PPIMV1)
2.3.41 Port P Input Register (PTIP)
Address 0x0259
Access: User read(1)
7
6
5
4
3
2
1
0
R
W
PTIP7
0
PTIP5
PTIP4
PTIP3
PTIP2
PTIP1
PTIP0
Reset
u
u
u
u
u
u
u
u
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-39. Port P Input Register (PTIP)
1. Read: Anytime
Write:Never, writes to this register have no effect.
Table 2-36. PTIP Register Field Descriptions
Field
Description
7,5-0
PTIP
Port P input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
2.3.42 Port P Data Direction Register (DDRP)
Address 0x025A
Access: User read/write(1)
7
6
5
4
3
2
1
0
R
W
0
DDRP7
DDRP5
DDRP4
DDRP3
DDRP2
DDRP1
DDRP0
Reset
0
0
0
0
0
0
0
0
Figure 2-40. Port P Data Direction Register (DDRP)
1. Read: Anytime
Write: Anytime
Table 2-37. DDRP Register Field Descriptions
Description
Field
7
Port P data direction—
DDRP
This bit determines whether the associated pin is an input or output.
1 Associated pin is configured as output
0 Associated pin is configured as input
S12P-Family Reference Manual, Rev. 1.13
88
Freescale Semiconductor
FREESCALE [ Freescale ]
