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MC9S12P64CFT 参数 Datasheet PDF下载

MC9S12P64CFT图片预览
型号: MC9S12P64CFT
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器 [Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 566 页 / 7414 K
品牌: FREESCALE [ Freescale ]
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Port Integration Module (S12PPIMV1)  
2.3.24 Port S Data Register (PTS)  
Address 0x0248  
Access: User read/write(1)  
7
6
5
4
3
2
1
0
R
0
0
0
0
PTS3  
PTS2  
PTS1  
PTS0  
W
Altern.  
Function  
0
0
0
0
0
0
TXD  
0
RXD  
0
Reset  
Figure 2-22. Port S Data Register (PTS)  
1. Read: Anytime The data source is depending on the data direction value.  
Write: Anytime  
Table 2-21. PTS Register Field Descriptions  
Field  
Description  
Port S general purpose input/output data—Data Register  
3-2  
PTS  
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general  
purpose output mode the register bit value is driven to the pin.  
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered  
pin input state is read.  
1
PTS  
Port S general purpose input/output data—Data Register, SCI TXD output  
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general  
purpose output mode the register bit value is driven to the pin.  
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered  
pin input state is read.  
• The SCI function takes precedence over the general purpose I/O function if enabled.  
0
PTS  
Port S general purpose input/output data—Data Register, SCI RXD input  
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general  
purpose output mode the register bit value is driven to the pin.  
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered  
pin input state is read.  
• The SCI function takes precedence over the general purpose I/O function if enabled.  
2.3.25 Port S Input Register (PTIS)  
Address 0x0249  
Access: User read(1)  
7
6
5
4
3
2
1
0
R
W
0
0
0
0
PTIS3  
PTIS2  
PTIS1  
PTIS0  
Reset  
u
u
u
u
u
u
u
u
= Unimplemented or Reserved  
u = Unaffected by reset  
Figure 2-23. Port S Input Register (PTIS)  
S12P-Family Reference Manual, Rev. 1.13  
Freescale Semiconductor  
77  
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