Port Integration Module (S12PPIMV1)
Table 2-15. PTIT Register Field Descriptions
Description
Field
7-0
Port T input data—
PTIT
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
2.3.18 Port T Data Direction Register (DDRT)
Address 0x0242
Access: User read/write(1)
7
6
5
4
3
2
1
0
R
W
DDRT7
DDRT6
DDRT5
DDRT4
DDRT3
DDRT2
DDRT1
DDRT0
Reset
0
0
0
0
0
0
0
0
Figure 2-16. Port T Data Direction Register (DDRT)
1. Read: Anytime
Write: Anytime
Table 2-16. DDRT Register Field Descriptions
Description
Field
7-6, 3-1 Port T data direction—
DDRT
This bit determines whether the pin is an input or output.
The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. In this case
the data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
5
Port T data direction—
DDRT
This bit determines whether the pin is an input or output.
The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. Else the
routed PWM forces the I/O state to be an output for an enabled channel. Else the API_EXTCLK forces the I/O state
to be an output if enabled. In these cases the data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
4,0
Port T data direction—
DDRT
This bit determines whether the pin is an input or output.
The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. Else the
routed PWM forces the I/O state to be an output for an enabled channel. In these cases the data direction bit will not
change.
1 Associated pin is configured as output
0 Associated pin is configured as input
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
73
FREESCALE [ Freescale ]
