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MC9S12P64CFT 参数 Datasheet PDF下载

MC9S12P64CFT图片预览
型号: MC9S12P64CFT
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器 [Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 566 页 / 7414 K
品牌: FREESCALE [ Freescale ]
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Port Integration Module (S12PPIMV1)  
2.3.29 Port S Polarity Select Register (PPSS)  
Address 0x024D  
Access: User read/write(1)  
7
6
5
4
3
2
1
0
R
W
0
0
0
0
PPSS3  
PPSS2  
PPSS1  
PPSS0  
Reset  
0
0
0
0
0
0
0
0
Figure 2-27. Port S Polarity Select Register (PPSS)  
1. Read: Anytime  
Write: Anytime  
Table 2-26. PPSS Register Field Descriptions  
Description  
Field  
3-0  
Port S pull device select—Configure pull device polarity on input pin  
PPSS  
This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.  
1 A pull-down device is selected  
0 A pull-up device is selected  
2.3.30 Port S Wired-Or Mode Register (WOMS)  
Address 0x024E  
Access: User read/write(1)  
7
6
5
4
3
2
1
0
R
W
0
0
0
0
WOMS3  
WOMS2  
WOMS1  
WOMS0  
Reset  
0
0
0
0
0
0
0
0
Figure 2-28. Port S Wired-Or Mode Register (WOMS)  
1. Read: Anytime  
Write: Anytime  
Table 2-27. WOMS Register Field Descriptions  
Description  
Field  
3-0  
Port S wired-or mode—Enable open-drain functionality on output pin  
WOMS  
This bit configures an output pin as wired-or (open-drain) or push-pull. In wired-or mode a logic “0” is driven active  
low while a logic “1” remains undriven. This allows a multipoint connection of several serial modules. The bit has no  
influence on pins used as input.  
1 Output buffer operates as open-drain output.  
0 Output buffer operates as push-pull output.  
S12P-Family Reference Manual, Rev. 1.13  
80  
Freescale Semiconductor  
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