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MC9S12P64CFT 参数 Datasheet PDF下载

MC9S12P64CFT图片预览
型号: MC9S12P64CFT
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器 [Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 566 页 / 7414 K
品牌: FREESCALE [ Freescale ]
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Port Integration Module (S12PPIMV1)  
2.3.19 Port T Reduced Drive Register (RDRT)  
Address 0x0243  
Access: User read/write(1)  
7
6
5
4
3
2
1
0
R
W
RDRT7  
RDRT6  
RDRT5  
RDRT4  
RDRT3  
RDRT2  
RDRT1  
RDRT0  
Reset  
0
0
0
0
0
0
0
0
Figure 2-17. Port T Reduced Drive Register (RDRT)  
1. Read: Anytime  
Write: Anytime  
Table 2-17. RDRT Register Field Descriptions  
Description  
Field  
7-0  
Port T reduced drive—Select reduced drive for output pin  
RDRT  
This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input  
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.  
1 Reduced drive selected (approx. 1/5 of the full drive strength)  
0 Full drive strength enabled  
2.3.20 Port T Pull Device Enable Register (PERT)  
Address 0x0244  
Access: User read/write(1)  
7
6
5
4
3
2
1
0
R
W
PERT7  
PERT6  
PERT5  
PERT4  
PERT3  
PERT2  
PERT1  
PERT0  
Reset  
0
0
0
0
0
0
0
0
Figure 2-18. Port T Pull Device Enable Register (PERT)  
1. Read: Anytime  
Write: Anytime  
Table 2-18. PERT Register Field Descriptions  
Description  
Field  
7-0  
Port T pull device enable—Enable pull device on input pin  
PERT  
This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has  
no effect. The polarity is selected by the related polarity select register bit.  
1 Pull device enabled  
0 Pull device disabled  
S12P-Family Reference Manual, Rev. 1.13  
74  
Freescale Semiconductor  
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