Port Integration Module (S12PPIMV1)
1. Read: Anytime
Write:Never, writes to this register have no effect.
Table 2-22. PTIS Register Field Descriptions
Field
Description
3-0
Port S input data—
PTIS
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
2.3.26 Port S Data Direction Register (DDRS)
Address 0x024A
Access: User read/write(1)
7
6
5
4
3
2
1
0
R
W
0
0
0
0
DDRS3
DDRS2
DDRS1
DDRS0
Reset
0
0
0
0
0
0
0
0
Figure 2-24. Port S Data Direction Register (DDRS)
1. Read: Anytime
Write: Anytime
Table 2-23. DDRS Register Field Descriptions
Description
Field
3-2
Port S data direction—
DDRS
This bit determines whether the associated pin is an input or output.
1 Associated pin is configured as output
0 Associated pin is configured as input
1
Port S data direction—
DDRS
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SCI the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
0
Port S data direction—
DDRS
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SCI the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
S12P-Family Reference Manual, Rev. 1.13
78
Freescale Semiconductor
FREESCALE [ Freescale ]
