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MC9S12P64CFT 参数 Datasheet PDF下载

MC9S12P64CFT图片预览
型号: MC9S12P64CFT
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器 [Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 566 页 / 7414 K
品牌: FREESCALE [ Freescale ]
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Port Integration Module (S12PPIMV1)  
2.3.27 Port S Reduced Drive Register (RDRS)  
Address 0x024B  
Access: User read/write(1)  
7
6
5
4
3
2
1
0
R
W
0
0
0
0
RDRS3  
RDRS2  
RDRS1  
RDRS0  
Reset  
0
0
0
0
0
0
0
0
Figure 2-25. Port S Reduced Drive Register (RDRS)  
1. Read: Anytime  
Write: Anytime  
Table 2-24. RDRS Register Field Descriptions  
Description  
Field  
3-0  
Port S reduced drive—Select reduced drive for output pin  
RDRS  
This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input  
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.  
1 Reduced drive selected (approx. 1/5 of the full drive strength)  
0 Full drive strength enabled  
2.3.28 Port S Pull Device Enable Register (PERS)  
Address 0x024C  
Access: User read/write(1)  
7
6
5
4
3
2
1
0
R
W
0
0
0
0
PERS3  
PERS2  
PERS1  
PERS0  
Reset  
0
0
0
0
1
1
1
1
Figure 2-26. Port S Pull Device Enable Register (PERS)  
1. Read: Anytime  
Write: Anytime  
Table 2-25. PERS Register Field Descriptions  
Description  
Field  
3-0  
Port S pull device enable—Enable pull device on input pin or wired-or output pin  
PERS  
This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has  
only effect if used in wired-or mode. The polarity is selected by the related polarity select register bit.  
1 Pull device enabled  
0 Pull device disabled  
S12P-Family Reference Manual, Rev. 1.13  
Freescale Semiconductor  
79  
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