Port Integration Module (S12PPIMV1)
Address 0x001F
Access: User read(1)
7
6
5
4
3
2
1
0
R
W
0
0
0
0
0
0
0
0
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-13. PIM Reserved Register
1. Read: Always reads 0x00
Write: Unimplemented
2.3.16 Port T Data Register (PTT)
Address 0x0240
Access: User read/write(1)
7
6
5
4
3
2
1
0
R
PTT7
PTT6
PTT5
PTT4
PTT3
PTT2
PTT1
PTT0
W
Altern.
Function
IOC7
—
IOC6
—
IOC5
(PWM5)
API_EXTCLK
0
IOC4
(PWM4)
—
IOC3
—
IOC2
—
IOC1
—
IOC0
(PWM0)
—
—
—
—
—
—
Reset
0
0
0
0
0
0
0
Figure 2-14. Port T Data Register (PTT)
1. Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
71
FREESCALE [ Freescale ]
