Port Integration Module (S12PPIMV1)
Address 0x001D
Access: User read(1)
7
6
5
4
3
2
1
0
R
W
0
0
0
0
0
0
0
0
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-11. PIM Reserved Register
1. Read: Always reads 0x00
Write: Unimplemented
2.3.14 IRQ Control Register (IRQCR)
Address 0x001E
Access: User read/write(1)
7
6
5
4
3
2
1
0
R
W
0
0
0
0
0
0
IRQE
IRQEN
Reset
0
1
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-12. IRQ Control Register (IRQCR)
1. Read: See individual bit descriptions below.
Write: See individual bit descriptions below.
Table 2-13. IRQCR Register Field Descriptions
Field
Description
7
IRQ select edge sensitive only—
Special mode: Read or write anytime.
Normal mode: Read anytime, write once.
IRQE
1 IRQ pin configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime IRQE=1
and will be cleared only upon a reset or the servicing of the IRQ interrupt.
0 IRQ pin configured for low level recognition
6
IRQ enable—
IRQEN
Read or write anytime.
1 IRQ pin is connected to interrupt logic
0 IRQ pin is disconnected from interrupt logic
2.3.15 PIM Reserved Register
This register is reserved for factory testing of the PIM module and is not available in normal operation.
Writing to this register when in special modes can alter the pin functionality.
S12P-Family Reference Manual, Rev. 1.13
70
Freescale Semiconductor
FREESCALE [ Freescale ]
