Port Integration Module (S12PPIMV1)
2.3.12 ECLK Control Register (ECLKCTL)
Address 0x001C
Access: User read/write(1)
7
6
5
4
3
2
1
0
R
NECLK
NCLKX2
DIV16
EDIV4
EDIV3
EDIV2
EDIV1
EDIV0
W
Mode
Depen-
dent
Reset:
1
0
0
0
0
0
0
Special
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
single-chip
Normal
single-chip
= Unimplemented or Reserved
Figure 2-10. ECLK Control Register (ECLKCTL)
1. Read: Anytime
Write: Anytime
Table 2-12. ECLKCTL Register Field Descriptions
Description
Field
7
No ECLK—Disable ECLK output
NECLK This bit controls the availability of a free-running clock on the ECLK pin. This clock has a fixed rate of equivalent to
the internal bus clock.
1 ECLK disabled
0 ECLK enabled
6
No ECLKX2—Disable ECLKX2 output
NCLKX2 This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the
internal bus clock.
1 ECLKX2 disabled
0 ECLKX2 enabled
5
Free-running ECLK pre-divider—Divide by 16
DIV16
This bit enables a divide-by-16 stage on the selected EDIV rate.
1 Divider enabled: ECLK rate = EDIV rate divided by 16
0 Divider disabled: ECLK rate = EDIV rate
4-0
Free-running ECLK Divider—Configure ECLK rate
EDIV
These bits determine the rate of the free-running clock on the ECLK pin.
00000 ECLK rate = bus clock rate
00001 ECLK rate = bus clock rate divided by 2
00010 ECLK rate = bus clock rate divided by 3,...
11111 ECLK rate = bus clock rate divided by 32
2.3.13 PIM Reserved Register
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
69
FREESCALE [ Freescale ]
