Port Integration Module (S12PPIMV1)
Table 2-2. Block Memory Map (continued)
Register
Offset or
Address
Port
Access Reset Value Section/Page
J
0x0268 PTJ—Port J Data Register
R/W
R
0x00
2.3.49/2-92
2.3.50/2-93
2.3.51/2-93
2.3.52/2-94
2.3.53/2-94
2.3.54/2-95
2.3.55/2-95
2.3.56/2-96
2.3.57/2-96
2.3.58/2-97
2.3.59/2-97
2.3.60/2-98
2.3.61/2-98
2.3.62/2-99
2.3.62/2-99
2.3.64/2-100
2.3.65/2-100
4
0x0269 PTIJ—Port J Input Register
0x026A DDRJ—Port J Data Direction Register
0x026B RDRJ—Port J Reduced Drive Register
0x026C PERJ—Port J Pull Device Enable Register
0x026D PPSJ—Port J Polarity Select Register
0x026E PIEJ—Port J Interrupt Enable Register
0x026F PIFJ—Port J Interrupt Flag Register
0x0270 PT0AD—Port AD Data Register
R/W
R/W
R/W
R/W
R/W
R/W
R
0x00
0x00
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
AD
0x0271 PT1AD—Port AD Data Register
R/W
R
0x0272 DDR0AD—Port AD Data Direction Register
0x0273 DDR1AD—Port AD Data Direction Register
0x0274 RDR0AD—Port AD Reduced Drive Register
0x0275 RDR1AD—Port AD Reduced Drive Register
0x0276 PER0AD—Port AD Pull Up Enable Register
0x0277 PER1AD—Port AD Pull Up Enable Register
R/W
R
R/W
R
R/W
R
0x0278 PIM Reserved
:
0x027F
1. Write access not applicable for one or more register bits. Refer to register description.
2. Refer to device memory map to determine related module.
3. Mode dependent.
4. Read always returns logic level on pins.
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x0000
PORTA
R
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PB1
PA0
W
0x0001
PORTB
R
PB7
PB6
PB5
PB4
PB3
PB2
PB0
W
0x0002
DDRA
R
DDRA7
DDRB7
DDRA6
DDRA5
DDRA4
DDRA3
DDRB3
DDRA2
DDRB2
DDRA1
DDRB1
DDRA0
DDRB0
W
0x0003
DDRB
R
DDRB6
DDRB5
DDRB4
W
= Unimplemented or Reserved
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
55
FREESCALE [ Freescale ]
