Port Integration Module (S12PPIMV1)
Table 2-2. Block Memory Map (continued)
Register
Offset or
Address
Port
Access Reset Value Section/Page
0x0004 PIM Reserved
R
0x00
2.3.7/2-65
:
0x0007
E
0x0008 PORTE—Port E Data Register
R/W(1)
R/W1
-
0x00
0x00
-
2.3.8/2-65
2.3.9/2-66
-
0x0009 DDRE—Port E Data Direction Register
0x000A Non-PIM address range(2)
:
0x000B
A
B
E
0x000C PUCR—Pull-up Up Control Register
0x000D RDRIV—Reduced Drive Register
R/W1
R/W1
0x50
0x00
2.3.10/2-67
2.3.11/2-68
0x000E Non-PIM address range2
-
-
-
:
0x001B
E
0x001C ECLKCTL—ECLK Control Register
0x001D PIM Reserved
R/W1 0xC0 / 0x80(3) 2.3.12/2-69
R
R/W1
R
0x00
0x40
0x00
-
2.3.13/2-69
2.3.14/2-70
2.3.15/2-70
-
0x001E IRQCR—IRQ Control Register
0x001F PIM Reserved
0x0020 Non-PIM address range2
-
:
0x023F
T
0x0240 PTT—Port T Data Register
R/W
R
0x00
2.3.16/2-71
2.3.17/2-72
2.3.18/2-73
2.3.19/2-74
2.3.20/2-74
2.3.21/2-75
2.3.22/2-75
2.3.23/2-76
(4)
0x0241 PTIT—Port T Input Register
0x0242 DDRT—Port T Data Direction Register
0x0243 RDRT—Port T Reduced Drive Register
0x0244 PERT—Port T Pull Device Enable Register
0x0245 PPST—Port T Polarity Select Register
0x0246 PIM Reserved
R/W
R/W
R/W
R/W
R
0x00
0x00
0x00
0x00
0x00
0x00
0x0247 Port T Routing Register
R/W
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
53
FREESCALE [ Freescale ]
