Port Integration Module (S12PPIMV1)
Pin Function
Port Pin Name
Pin Function
after Reset
I/O
Description
& Priority(1)
M
PM5
PM4
PM3
SCK
GPIO
MOSI
GPIO
SS
I/O Serial Peripheral Interface serial clock pin
I/O General purpose
GPIO
I/O Serial Peripheral Interface master out/slave in pin
I/O General purpose
I/O Serial Peripheral Interface slave select output in master mode,
input in slave mode or master mode.
GPIO
MISO
I/O General purpose
PM2
PM1
PM0
I/O Serial Peripheral Interface master in/slave out pin
I/O General purpose
GPIO
TXCAN
GPIO
O
MSCAN transmit pin
I/O General purpose
MSCAN receive
RXCAN
GPIO
I
I/O General purpose
P
PP7
PP5
GPIO/KWP7
PWM5
I/O General purpose; with interrupt
I/O Pulse Width Modulator channel 5; emergency shut-down
I/O General purpose; with interrupt
GPIO
GPIO/KWP5
PWM[4:0]
PP[4:0]
O
Pulse Width Modulator channel 4 - 0
GPIO/KWP[4:0] I/O General purpose; with interrupt
GPIO/KWJ[7:6] I/O General purpose; with interrupt
GPIO/KWJ[2:0] I/O General purpose; with interrupt
J
PJ[7:6]
PJ[2:0]
GPIO
GPIO
AD
PAD[9:0]
GPIO
I/O General purpose
AN[9:0]
I
ATD analog
1. Signals in brackets denote alternative module routing pins.
2. Function active when RESET asserted.
2.3
Memory Map and Register Definition
This section provides a detailed description of all Port Integration Module registers.
2.3.1
Memory Map
Table 2-2 shows the register map of the Port Integration Module.
Table 2-2. Block Memory Map
Offset or
Address
Port
Register
Access Reset Value Section/Page
A
B
0x0000 PORTA—Port A Data Register
R/W
R/W
R/W
R/W
0x00
0x00
0x00
0x00
2.3.3/2-63
2.3.4/2-63
2.3.5/2-64
2.3.6/2-64
0x0001 PORTB—Port B Data Register
0x0002 DDRA—Port A Data Direction Register
0x0003 DDRB—Port B Data Direction Register
S12P-Family Reference Manual, Rev. 1.13
52
Freescale Semiconductor
FREESCALE [ Freescale ]
