Timer Module (TIM16B8CV2) Block Description
14.3.2.15 16-Bit Pulse Accumulator Control Register (PACTL)
Module Base + 0x0020
7
6
5
4
3
2
1
0
R
W
0
PAEN
PAMOD
PEDGE
CLK1
CLK0
PAOVI
PAI
Reset
0
0
0
0
0
0
0
0
Unimplemented or Reserved
Figure 14-24. 16-Bit Pulse Accumulator Control Register (PACTL)
When PAEN is set, the PACT is enabled.The PACT shares the input pin with IOC7.
Read: Any time
Write: Any time
Table 14-17. PACTL Field Descriptions
Field
Description
6
Pulse Accumulator System Enable — PAEN is independent from TEN. With timer disabled, the pulse
accumulator can function unless pulse accumulator is disabled.
0 16-Bit Pulse Accumulator system disabled.
PAEN
1 Pulse Accumulator system enabled.
5
Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1). See
PAMOD
Table 14-18.
0 Event counter mode.
1 Gated time accumulation mode.
4
Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1).
For PAMOD bit = 0 (event counter mode). See Table 14-18.
PEDGE
0 Falling edges on IOC7 pin cause the count to be incremented.
1 Rising edges on IOC7 pin cause the count to be incremented.
For PAMOD bit = 1 (gated time accumulation mode).
0 IOC7 input pin high enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing falling
edge on IOC7 sets the PAIF flag.
1 IOC7 input pin low enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing rising edge
on IOC7 sets the PAIF flag.
3:2
Clock Select Bits — Refer to Table 14-19.
CLK[1:0]
1
Pulse Accumulator Overflow Interrupt Enable
0 Interrupt inhibited.
PAOVI
1 Interrupt requested if PAOVF is set.
0
PAI
Pulse Accumulator Input Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAIF is set.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
491
FREESCALE [ Freescale ]
