Timer Module (TIM16B8CV2) Block Description
14.3.2.18 Output Compare Pin Disconnect Register(OCPD)
Module Base + 0x002C
7
6
5
4
3
2
1
0
R
W
OCPD7
OCPD6
OCPD5
OCPD4
OCPD3
OCPD2
OCPD1
OCPD0
Reset
0
0
0
0
0
0
0
0
Figure 14-28. Ouput Compare Pin Disconnect Register (OCPD)
Read: Anytime
Write: Anytime
All bits reset to zero.
Table 14-21. OCPD Field Description
Description
Field
Output Compare Pin Disconnect Bits
OCPD[7:0} 0 Enables the timer channel port. Ouptut Compare action will occur on the channel pin. These bits do not affect
the input capture or pulse accumulator functions
1 Disables the timer channel port. Output Compare action will not occur on the channel pin, but the output
compare flag still become set .
14.3.2.19 Precision Timer Prescaler Select Register (PTPSR)
Module Base + 0x002E
7
6
5
4
3
2
1
0
R
W
PTPS7
PTPS6
PTPS5
PTPS4
PTPS3
PTPS2
PTPS1
PTPS0
Reset
0
0
0
0
0
0
0
0
Figure 14-29. Precision Timer Prescaler Select Register (PTPSR)
Read: Anytime
Write: Anytime
All bits reset to zero.
S12P-Family Reference Manual, Rev. 1.13
494
Freescale Semiconductor
FREESCALE [ Freescale ]
