Timer Module (TIM16B8CV2) Block Description
14.3.2.10 Timer Interrupt Enable Register (TIE)
Module Base + 0x000C
7
6
5
4
3
2
1
0
R
W
C7I
C6I
C5I
C4I
C3I
C2I
C1I
C0I
Reset
0
0
0
0
0
0
0
0
Figure 14-18. Timer Interrupt Enable Register (TIE)
Read: Anytime
Write: Anytime.
Table 14-12. TIE Field Descriptions
Description
Field
7:0
C7I:C0I
Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in
the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set,
the corresponding flag is enabled to cause a interrupt.
14.3.2.11 Timer System Control Register 2 (TSCR2)
Module Base + 0x000D
7
6
5
4
3
2
1
0
R
W
0
0
0
TOI
TCRE
PR2
PR1
PR0
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-19. Timer System Control Register 2 (TSCR2)
Read: Anytime
Write: Anytime.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
487
FREESCALE [ Freescale ]
