Timer Module (TIM16B8CV2) Block Description
Table 14-22. PTPSR Field Descriptions
Field
Description
7:0
Precision Timer Prescaler Select Bits — These eight bits specify the division rate of the main Timer prescaler.
PTPS[7:0] These are effective only when the PRNT bit of TSCR1 is set to 1. Table 14-23 shows some selection examples
in this case.
The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter
stages equal zero.
The Prescaler can be calculated as follows depending on logical value of the PTPS[7:0] and PRNT bit:
PRNT = 1 : Prescaler = PTPS[7:0] + 1
Table 14-23. Precision Timer Prescaler Selection Examples when PRNT = 1
Prescale
PTPS7
PTPS6
PTPS5
PTPS4
PTPS3
PTPS2
PTPS1
PTPS0
Factor
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
2
3
4
5
6
7
8
16
32
64
128
256
14.4 Functional Description
This section provides a complete functional description of the timer TIM16B8CV2 block. Please refer to
the detailed timer block diagram in Figure 14-30 as necessary.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
495
FREESCALE [ Freescale ]
