Timer Module (TIM16B8CV2) Block Description
Table 14-13. TSCR2 Field Descriptions
Field
Description
7
Timer Overflow Interrupt Enable
TOI
0 Interrupt inhibited.
1 Hardware interrupt requested when TOF flag set.
3
Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful output compare 7
event. This mode of operation is similar to an up-counting modulus counter.
0 Counter reset inhibited and counter free runs.
TCRE
1 Counter reset by a successful output compare 7.
If TC7 = 0x0000 and TCRE = 1, TCNT will stay at 0x0000 continuously. If TC7 = 0xFFFF and TCRE = 1, TOF
will never be set when TCNT is reset from 0xFFFF to 0x0000.
2
Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the
PR[2:0]
Bus Clock as shown in Table 14-14.
Table 14-14. Timer Clock Selection
PR2
PR1
PR0
Timer Clock
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Bus Clock / 1
Bus Clock / 2
Bus Clock / 4
Bus Clock / 8
Bus Clock / 16
Bus Clock / 32
Bus Clock / 64
Bus Clock / 128
NOTE
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
14.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)
Module Base + 0x000E
7
6
5
4
3
2
1
0
R
W
C7F
C6F
C5F
C4F
C3F
C2F
C1F
C0F
Reset
0
0
0
0
0
0
0
0
Figure 14-20. Main Timer Interrupt Flag 1 (TFLG1)
Read: Anytime
Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero
will not affect current status of the bit.
S12P-Family Reference Manual, Rev. 1.13
488
Freescale Semiconductor
FREESCALE [ Freescale ]
